In reply to Aswin_VA:
While you may not have signals on the bus to represent the FSM state, I’m sure there’s a bit-vector somewhere that does. You could create a separate SV interface with a set of signals bound to the FSM vector. Then, you could treat this just like any other interface and write a monitor for it. The monitor could sense when the state changes and report that as a transaction via its analysis port. The real question to ask yourself is what you want to do with the information. If it will be used to control some other aspect of the testbench, or even to be recorded in a covergroup, then this interface-monitor approach would be fine. If all you want to do is to make sure that you don’t take any illegal transitions, then using assertions is probably the best way. Then you can use formal to guarantee the correctness of your FSM and you don’t need to worry about it in your UVM testbench.