UVM_FATAL ----> send_request failed to cast sequence item

UVM
,
1

i am creating a virtual sequence and calling from a test case but, getting fatal error in simulation as below:
UVM_FATAL @ 10: uvm_test_top.h_env.agn2.m_sequencer [m_sequencer] send_request failed to cast sequence item

please, let me know what am i doing wrong ?

for the following code:

/////////////////////////////////////////////////////////
////////// Virtual sequence base class //////////////////
/////////////////////////////////////////////////////////
class axi_virtual_base extends uvm_sequence #(uvm_sequence_item) ;
	
	`uvm_object_utils(axi_virtual_base)
	
	uvm_sequencer #(axi_packet) 	  m_seqr ;
	uvm_sequencer #(axi_slave_packet) s_seqr ;

	function new(string name = "axi_virtual_base") ;
		super.new(name) ;
	endfunction	
endclass : axi_virtual_base

///////////////////////////////////////////////////////////////////////////////////////////
/////////////// virtual sequence class extended from virtual sequence base class //////////
///////////////////////////////////////////////////////////////////////////////////////////
class axi_virtual_sequence extends axi_virtual_base ;
	
	`uvm_object_utils(axi_virtual_sequence)
	
	function new(string name = "axi_virtual_sequence");
		super.new(name);
	endfunction
	
	axi_master_sequence_reset ms_reset ;
	axi_slave_sequence_reset  ss_reset ;
	
	task body() ;
		ms_reset = axi_master_sequence_reset::type_id::create("ms_reset") ;
		ss_reset = axi_slave_sequence_reset::type_id::create("ss_reset")  ;
		fork
			ms_reset.start(m_seqr) ;                                          // NEED
			ss_reset.start(s_seqr) ;                                          // HELP HERE
			$display ("@time -> %0t in virtual test case fork-join",$time) ;  // THE SIMULATION STOPS WITH THE ABOVE MENTION FATAL ERROR.
		join
		$display ("@time -> %0t out from fork-join",$time) ;
	endtask : body

endclass : axi_virtual_sequence

/////////////////////////////////////////////
/////////// base test code //////////////////
/////////////////////////////////////////////
class axi_test_base extends uvm_test;

	`uvm_component_utils(axi_test_base)

	axi_environment         	h_env  ;
	
	function new(string name = "axi_test_base", uvm_component parent = null);
		super.new(name, parent);
	endfunction
	
	function void build_phase(uvm_phase phase);
		super.build_phase(phase) ;
		h_env   = axi_environment::type_id::create("h_env",this)        ;
	endfunction : build_phase
	
        /////// initialization of sequencer handles ///////////
	virtual function void init_vseq(axi_virtual_base avb) ;
			avb.m_seqr = h_env.agn1.m_sequencer ;
			avb.s_seqr = h_env.agn2.m_sequencer ;
	endfunction : init_vseq
	
        ///////// base run phase is empty ////////////////////
	virtual task run_phase(uvm_phase phase)            		   ;
		uvm_report_info(get_full_name(),"run",UVM_LOW) ;
    	
		phase.raise_objection(this)                    ;

		phase.drop_objection(this)                     ;
		
	endtask : run_phase

endclass : axi_test_base

////////////////////////////////////////////////////////////////////////////
//////////////// test case extended from base test - reset /////////////////
////////////////////////////////////////////////////////////////////////////
class axi_test_case_reset extends axi_test_base ;

	`uvm_component_utils(axi_test_case_reset)
	
	axi_virtual_sequence avs ;
	
	function new(string name = "axi_test_case_reset", uvm_component parent = null) ;
		super.new(name, parent) ;
	endfunction
	
	task run_phase(uvm_phase phase) ;

		uvm_report_info(get_full_name(),"run",UVM_LOW) ;

		avs = axi_virtual_sequence::type_id::create("avs") ;

		phase.raise_objection(this) ;
			init_vseq(avs)  ; ////// calling initialization function in base test ///////
			avs.start(null) ; ////// starting the virtual sequence ////////
		phase.drop_objection(this) ;
	endtask : run_phase

endclass : axi_test_case_reset
2

Not enough code shown to help you. You need to double-check that all classes involved in the flow of the sequence_item are parameterized correctly, and the uvm_objects_utils have the correct class name. (in drivers, sequencers, agents).

Also, when you start a sequence in a virtual sequence, set the parent argument to ‘this’;

3

In reply to dave_59:

here are some of master side codes, hope this helps → 


//-------------------------------------------------------------------------------------//
// The reset sequence //
//-------------------------------------------------------------------------------------//
class axi_master_sequence_reset extends uvm_sequence #(axi_packet);

	`uvm_object_utils(axi_master_sequence_reset)
	
	function new(string name = "axi_master_sequence_reset");
		super.new(name);
	endfunction
	
	virtual task body();
		axi_packet pkt_reset;
		pkt_reset = axi_packet::type_id::create("pkt_reset");
		start_item(pkt_reset);
			assert(pkt_reset.randomize() 
				with
					{	
						ARESETn == 0        ;
					});
		finish_item(pkt_reset)			    ;
	endtask : body

endclass : axi_master_sequence_reset

//-------------------------------------------------------------------------------------//
// The master axi agent //
//-------------------------------------------------------------------------------------//
class axi_master_agent extends uvm_agent ;
	
	`uvm_component_utils(axi_master_agent)
	
	axi_master_driver    drv  ;
	axi_master_monitor   mon  ;
	
        /////// HERE IS PARAMETERIZED  SEQUENCER //////
	uvm_sequencer #(axi_packet) m_sequencer ;
	
	uvm_analysis_port #(axi_packet) aport ;
	
	function new(string name, uvm_component parent) ;
		super.new(name, parent)                       ;
	endfunction
	
	function void build_phase(uvm_phase phase)             ;
		aport 		  = new("aport", this)						            ;
		drv   		  = axi_master_driver::type_id::create("drv", this)     ;
		mon   		  = axi_master_monitor::type_id::create("mon", this)    ;

                ///////////////////// CREATING THE SEQUENCER /////////////////////////////
		m_sequencer   = uvm_sequencer #(axi_packet)::type_id::create("m_sequencer", this)    ;
	endfunction : build_phase
	
	function void connect_phase(uvm_phase phase)        ;
		///////////// sending through m_sequencer ///////////////
		drv.seq_item_port.connect(m_sequencer.seq_item_export) ;

		// this is pass through type analysis port implementation
		mon.aport.connect(aport);
	endfunction : connect_phase

endclass : axi_master_agent

///////////////////////////////////////////////////////////////////////////////
// Class axi_master_driver: this class contains bus functional model for AXI (master side)
///////////////////////////////////////////////////////////////////////////////
class axi_master_driver extends uvm_driver #(axi_packet);

	`uvm_component_utils(axi_master_driver)
	
	virtual axi_master_interface axi_inf ;

        function new(string name, uvm_component parent);
		super.new(name, parent);
	endfunction
	
	function void build_phase(uvm_phase phase) ;
	  uvm_config_db #(virtual axi_master_interface)::get(this,"","axi_ms",axi_inf) ;
        endfunction : build_phase

        virtual task run_phase(uvm_phase phase);

          //////..............some statements..... /////
          @(posedge axi_inf.ACLK);

        	seq_item_port.get_next_item(n_pkt);
                 //////..............some statements..... /////

		`uvm_info("master_driver_run_phase", n_pkt.sprint(), UVM_MEDIUM)
                 //////..............some statements..... /////

                 seq_item_port.item_done()

        endtask : run_phase

           //////.............. rest of the BFM ..... /////

endclass : axi_master_driver
4

In reply to piyushpatel40:

hey !
thanks Dave, double checked every thing and found the mistake, silly mistake though:

in the packet class one of the variable was not declared as rand → and i was randomizing the packet handle in the sequence class → and running this in the virtual sequence causes the cast error during simulation.