UVM_FATAL ----> send_request failed to cast sequence item

UVM
,
3

In reply to dave_59:

here are some of master side codes, hope this helps → 


//-------------------------------------------------------------------------------------//
// The reset sequence //
//-------------------------------------------------------------------------------------//
class axi_master_sequence_reset extends uvm_sequence #(axi_packet);

	`uvm_object_utils(axi_master_sequence_reset)
	
	function new(string name = "axi_master_sequence_reset");
		super.new(name);
	endfunction
	
	virtual task body();
		axi_packet pkt_reset;
		pkt_reset = axi_packet::type_id::create("pkt_reset");
		start_item(pkt_reset);
			assert(pkt_reset.randomize() 
				with
					{	
						ARESETn == 0        ;
					});
		finish_item(pkt_reset)			    ;
	endtask : body

endclass : axi_master_sequence_reset

//-------------------------------------------------------------------------------------//
// The master axi agent //
//-------------------------------------------------------------------------------------//
class axi_master_agent extends uvm_agent ;
	
	`uvm_component_utils(axi_master_agent)
	
	axi_master_driver    drv  ;
	axi_master_monitor   mon  ;
	
        /////// HERE IS PARAMETERIZED  SEQUENCER //////
	uvm_sequencer #(axi_packet) m_sequencer ;
	
	uvm_analysis_port #(axi_packet) aport ;
	
	function new(string name, uvm_component parent) ;
		super.new(name, parent)                       ;
	endfunction
	
	function void build_phase(uvm_phase phase)             ;
		aport 		  = new("aport", this)						            ;
		drv   		  = axi_master_driver::type_id::create("drv", this)     ;
		mon   		  = axi_master_monitor::type_id::create("mon", this)    ;

                ///////////////////// CREATING THE SEQUENCER /////////////////////////////
		m_sequencer   = uvm_sequencer #(axi_packet)::type_id::create("m_sequencer", this)    ;
	endfunction : build_phase
	
	function void connect_phase(uvm_phase phase)        ;
		///////////// sending through m_sequencer ///////////////
		drv.seq_item_port.connect(m_sequencer.seq_item_export) ;

		// this is pass through type analysis port implementation
		mon.aport.connect(aport);
	endfunction : connect_phase

endclass : axi_master_agent

///////////////////////////////////////////////////////////////////////////////
// Class axi_master_driver: this class contains bus functional model for AXI (master side)
///////////////////////////////////////////////////////////////////////////////
class axi_master_driver extends uvm_driver #(axi_packet);

	`uvm_component_utils(axi_master_driver)
	
	virtual axi_master_interface axi_inf ;

        function new(string name, uvm_component parent);
		super.new(name, parent);
	endfunction
	
	function void build_phase(uvm_phase phase) ;
	  uvm_config_db #(virtual axi_master_interface)::get(this,"","axi_ms",axi_inf) ;
        endfunction : build_phase

        virtual task run_phase(uvm_phase phase);

          //////..............some statements..... /////
          @(posedge axi_inf.ACLK);

        	seq_item_port.get_next_item(n_pkt);
                 //////..............some statements..... /////

		`uvm_info("master_driver_run_phase", n_pkt.sprint(), UVM_MEDIUM)
                 //////..............some statements..... /////

                 seq_item_port.item_done()

        endtask : run_phase

           //////.............. rest of the BFM ..... /////

endclass : axi_master_driver