New expanded support for the Universal Verification Methodology (UVM).
The UVM delivers productivity gains made possible by reuse in functional verification. For some verification teams, the hurdle to implement a UVM-based verification environment is simply getting started. To eliminate that hurdle, Mentor introduces UVM Express, a way to progressively adopt a UVM methodology.
Other verification teams have an established UVM-based verification environment, but are challenged to move their trusted verification approach up in abstraction where a new level of system verification can be achieved.
For those verification teams, Mentor introduces UVM Connect, which provides standard TLM 1.0 and TLM 2.0 connectivity between models written in SystemC and UVM SystemVerilog as well as the ability for SystemC environments to control UVM simulation in SystemVerilog.
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New Modules: Advanced UVM & UVM Express.
The Advanced UVM module hosted by Tom Fitzpatrick consists of 10 sessions, providing close to 3 hours of material that builds on the concepts covered in the Basic UVM module to take your UVM understanding to the next level.
Learn more about Advanced UVM.
The UVM Express module hosted by Rich Edelman is a collection of techniques, coding styles and UVM usages that are designed to increase the productivity of functional verification. If you don't have a full-time verification expert on staff, or if you are not a full-time verification engineer, the UVM Express module's 3 sessions might be for you.
Learn more about UVM Express.