Advanced UVM (Universal Verification Methodology)
The Advanced UVM (Universal Verification Methodology) module consists of 10 sessions, providing close to 3 hours of material that builds on the concepts covered in the Basic UVM Module to take your UVM understanding to the next level. You will learn how to build tests and verification environments, understand how to use the factory and configuration database to customize your verification IP, and how to create reusable stimulus sequences, including for multi-layer protocols. We will also introduce the UVM Register layer, showing you how to create a register model and how to write and reuse tests register level tests.
The target audience for this module is:
- Walk - content is of general interest, particularly to managers, but also engineers.
- Run - content is technical in nature, and of interest to engineers.
Recommended Prerequisite:
- Architecting a UVM Testbench
- Customization: Understanding the Factory and Configuration
- How TLM Works
- Modeling Transactions
- The Proper Care and Feeding of Sequences
- Layered Sequences
- Writing and Managing Tests
- Setting Up the Register Layer
- Using the Register Layer
- Register-Based Testing
This session covers the basic architecture of a UVM testbench, including the introduction of the Agent/UVC component that encapsulates protocol-specific interactions with the DUT. It also shows how to instantiate and connect multiple components.
This session shows how tests can use the factory to control the type of components that get instantiated in a UVM environment and how to write environments and components to support customization. It covers the configuration database that allows tests to override configuration information used by environments and components.
This session discusses the use of transaction-level modeling interfaces in UVM to facilitate the creation of modular, hierarchical components. It also covers the design and creation of scoreboard components.
This session outlines the methods needed in the design of a sequence item (a.k.a. “transaction) for use in UVM. It also discusses transaction extension a encapsulation to create more complex transactions.
This session covers the creation and execution of sequences, including the interaction of the sequence and driver. It includes the execution of sequential, parallel and hierarchical subsequences.
This session shows how to create a virtual sequence, which controls the execution of other sequences. It also discusses how to model layered protocols and encapsulate the layering components in a UVC.
This session shows how to create a set of tests derived from a base test that defines the default setup of your environment, including how to invoke specific tests from the command line. It also covers how to use phase objections to manage the execution of the test.
This session introduces the UVM Register Layer, showing you how to create register models that reflect the operation of the hardware registers in your DUT. It shows how to set up the address map of registers and how to convert a register-level transaction into a bus-level transaction. It also shows how the Register Assistant tool in Certe Testbench Studio can be used to create correct-by-construction register models from a specification.
This session discusses the various methods that a test can use to access the register model, including both “front-door” and “back-door” accesses. It also shows how to create register-bases stimulus sequences to simplify the API.
This session shows how to round out your register-based test environment with register-level scoreboards and functional coverage. It also shows how to create memory-based sequences.