Uvm_event ordering

UVM
,
1

I am using UVM event to monitor interrupt in my Testebench. I have 3 such interrupts. Now I want to make sure that they are asserted in a certain order.
SV events have wait_order to do so. Is there a way to do it using uvm_event?

2

Unfortunately, uvm_event is a very thick wrapper around a SystemVerilog event. You can either use a SystemVerilog event directly, or use the uvm_event to trigger an SystemVerilog event. Then you wil be able to use wait_order.

3

Yeah, Its very ugly. Any other thought on how can this be dealt with?

I am trying to validate ordering of a three bit interrupt whose triggering levels are configurable for each bit.

4

You would need to explain why my other suggestions do not work for you.