We are currently embarking on defining our UVM verification enviroment.
Now i know that the UVM methodology is based around the SystemVerilog class structure.
Therefore, the logical step to build a UVM compliant verification environment would be to model and build the environment in System Verilog.
However, in our verification team, most of the expertise is in Specman 'e. Therefore, they are thinking of building the verification components in Specman ‘e’ and then interfacing to the UVM class library. As a first thought, this seems like doing extra work to interface Specman ‘e’ code to UVM class library.
QS:
Has anyone else used this approach and if so that are their thoughts on how easy/difficult/suitable it is?
Does anyone have thoughts whether this approach makes sense or not?
If you have existing e VIP, then there are ways to integrate those components via pins of the DUT, or as transactions using the DPI. However, if you are starting from scratch, you best bet is to use the UVM with SystemVerilog in the manner that it was designed for. It will be much more efficient that way, and re-usable in the long term.
UVM was derived from URM (Cadence) and AVM (Mentor). The URM methodology was based almost entirely around the functionality composing the eRM (e Reuse Methodology). The UVM class library is required in order to bring added productivity gains to SystemVerilog. Even with the class libraries added, the SystemVerilog language is not as powerful or as compact as e so one begs the question … If your expertise is in e, why are you considering moving to a less powerful language?
Now, interfacing e components to SV components can be done in a number of ways depending on the level of communication you need between the components. For example, if all you need to do is take a transaction in e and push it to SV, there are several ways to do this (calling verilog tasks/functions, dumping to memory, method ports, etc.). If you are looking for more control (co-ordinating traffic generation across multiple sequence drivers in different languages and/or generating a topology configuration in one language (say e) and building the SV environment based based on the configuration) then you may need to tap into the Multi-Language infrastructure of your EDA Simulator. I know that at least Cadence does supply this infrastructure. The industry is moving towards a standard Multi-Language methodology however, we aren’t quite there yet.
My suggestion to you would be to really question why your team is considering moving to SV at all. If you must move, then talk to your EDA vendor about their ML solutions that you can take advantage of.
Our company wide policy is for all the IP groups to move to a UVM compliant validation environment. Our SOC group has the expertise in Specman ‘e’ and they have built all their validation environemnts in ‘e’ interfacing to OVM/UVM.
Management wants us to uild the validation environment in SystemVerilog and move aways from ‘e’.
Hi DAV,
As you have mentioned here “If you have existing e VIP, then there are ways to integrate those components via pins of the DUT, or as transactions using the DPI.”
Can you please explain how actually we can make it possible.
In my scenario I have an E VIP but the Scoreboard , Coverage Model , Test-cases and Sequences I want to Write in UVM. So here i have VIP of APB bus which is written in SPECMAN but I want to run the test-cases using UVM enviroment and want to have scoreboard and coverage model in UVM. SO can it be possible?