During any test case execution in UVM; we first get the UVM Component hierarchy printed in the terminal; like First Environment handle then Agent handle then Driver, Sequence, Sequencer and Monitor handles etc. Is there any way to get the print for connection information of Connect Phase i.e. the connection of Sequencer handle with Driver handle using TLM ranging from Test to End Driver? Or we need to debug it by opening every files ranging from Test bench Top to the End Driver?
For me it is nor clear what the intention of your question is. Do you want to know whether your UVM testbench is complete, containg all components and connections? print_topology is printing the whole topology of your testbench.
In complex SoC verification there are multiple environments, virtual sequencers, multiple agents, drivers, sequencers, sequences etc. The handles of these components are created and connected as per configurations we passed in the Test Case.
My intention is to know which component is created and connected after execution of the test case. For example : In the test case if we run one sequence on virtual sequencer; which contains multiple sequencer handles in multiple agents; now multiple agents contains multiple drivers. So if I can know the all connect phase information of all agents inside the Test Bench after any Test Case execution; I can understand the Test Bench better. I can understand the whole TLM communication flow ranging from Test to the End Driver.
Is there any method to get the above information printed?
Hi Vishal,
the UVM is a very structured and regular approach. Each agent consists of a sequencer/driver pair and you might have also a monitor there. An env consists of a couple of agents, one or more scoreboards and mybe coverage collectors. A test customizes your env to the needs for testing a certain functionality in your DUT.
The UVM provides you a couple of methods to investigaate your UVM environment. But you have always to insert in your code additional debugging constructs. I mentioned in my last reply ‘print_topology’. With respect to the connections look at the uvm_port_base construct in the UVM ref. manual. But this extends always the amount of your code and might have influence on the performance of your simulation. The question is if this is really what you want.
If you want to understand your code I recommend a visual inspection of all testbench components.
You’ll see and understand the regularity of the code and the testbench.