In reply to chr_sue:
In complex SoC verification there are multiple environments, virtual sequencers, multiple agents, drivers, sequencers, sequences etc. The handles of these components are created and connected as per configurations we passed in the Test Case.
My intention is to know which component is created and connected after execution of the test case. For example : In the test case if we run one sequence on virtual sequencer; which contains multiple sequencer handles in multiple agents; now multiple agents contains multiple drivers. So if I can know the all connect phase information of all agents inside the Test Bench after any Test Case execution; I can understand the Test Bench better. I can understand the whole TLM communication flow ranging from Test to the End Driver.
Is there any method to get the above information printed?
Thanks,
Vishal