Uvm_config_db - virtual interface

Hello all,
What is the reason we use “virtual” word when send the interfaces from test bench to UVM enviroment?

module x_top;

 interface x_if();
 logic data, clock, reset;
 endinterface: x_if

x_if x_if_inst;

initial begin
uvm_config_db#(virtual x_if)::set(uvm_root::get(), "*", "x_vif", x_if_inst);


Thanks !

In reply to mago1991:

The use of a virtual interface is a core concept in SystemVerilog that connects a class based environment to an instance based environment. I recommend you review the UVM Basics course to better understand this concept.