Hello all,
What is the reason we use “virtual” word when send the interfaces from test bench to UVM enviroment?
module x_top;
...
interface x_if();
logic data, clock, reset;
endinterface: x_if
...
x_if x_if_inst;
initial begin
uvm_config_db#(virtual x_if)::set(uvm_root::get(), "*", "x_vif", x_if_inst);
...
run_test();
end
...
endmodule
Thanks !