Hi All,
I am trying to create a UVM clock UVC which can generate N#of clocks based on the parameter we set. I generate these clocks in the interface which receives the frequency information from the driver. I am using a “generate” to repeat the always statement based on the set parameter. However, I am unable to change the frequency of these clocks during the course of the simulation. I understand that I cannot use “freq” which is real number in the sensitivity list of always statement inside the generate block. How can I handle this scenario? I am OK with moving away from generate block and using any other method to generate parameterized number of clocks; however, I definitely want to have a capability of changing the clock frequency in the middle of the simulation(through sequence).
Any help would be appreciated.
//Interface
logic [CLK_NUM-1:0] clk_out ;
logic [CLK_NUM-1:0] enable ;
int freq[CLK_NUM] ;
int duty[CLK_NUM] ;
int phase[CLK_NUM] ;
real freq_Ghz[CLK_NUM-1:0] ; //Variable to store Ghz converted frequency
real Tperiod [CLK_NUM-1:0] ; //Timeperiod
real half_Tperiod[CLK_NUM-1:0] ; //half the Time period
real temp_freq[CLK_NUM-1:0] ; //Temp storage for the frequency
logic [CLK_NUM-1:0] update_freq;
initial begin
enable [CLK_NUM-1:0] =0;
clk_out[CLK_NUM-1:0] =0;
end
genvar c;
generate
for( c = 0 ; c < CLK_NUM ; c++) begin
always @(posedge enable[c] or negedge enable[c]) begin
$display ("I am in the block %t",$time);
if(enable[c] == 1 ) begin
freq_Ghz[c] = freq[c] * 0.001;
Tperiod[c] = 1.0/freq_Ghz[c];
half_Tperiod[c] = Tperiod[c]/2.0;
forever begin
#(half_Tperiod[c]) clk_out[c] = ~clk_out[c];
end
end
else begin
clk_out[c] =0;
end
end
end
endgenerate