UVM Clock agent to create parameterized number of clock, either of which can during course of the simulation

UVM
3

I set it from driver.

task clk_driver::get_and_drive();

  `uvm_info(get_type_name(), "Reset dropped", UVM_LOW)
  forever begin
    clk_seq_item req;             
    seq_item_port.get_next_item(req);
    // Drive the data item
    `uvm_info(get_type_name(), $sformatf("Driving master_transaction :\n%s",req.sprint()), UVM_LOW)
    vif.enable = req.enable;      //Enabling 
    vif.freq   = req.freq  ;
    vif.duty   = req.duty  ;
    vif.phase  = req.phase ;
    
    seq_item_port.item_done();
  end


endtask : get_and_drive