Uvm_backdoor and uvm_frontdoor parallel access to a register

I am having one scenario where reg write is happening thru frontdoor access in one uvm_component run_phase. We know It takes couple of clock cycles to complete. For example I am initiating write at 50ns sim time and it is completing at 100ns. At 80ns I am seeing the DUT register signal is going 0->1 as I am writing 1 to that register (reset value is 0) .
In another uvm_component run_phase I am reading the particular register signal using backdoor access for every clock cycle. But the read is skipping the backdoor access(50ns to 100ns cycle) during the write process of the same register. Is it possible to read the register at 80ns at the clock edge?.Please help.


In reply to debdip microsemi:

First, you are mixing 2 things frontdoor sequence and frontdoor access. These are 2 different things.
second, you have a vild value in your register if the access has been completed. But you want to read via backdoor when the frontdoor access is still not ready. The UVM mechanism is helping you to avoid such an invalid access.

In reply to chr_sue:

I have a similar issue. I am doing a front-door field write which takes a long time to return. While that is happening I want to poll the DUT register bit with back-door field reads (peek) so I can verify a Read Write Self Clear register is working. Is there a way to do back-door peeks in parallel with front-door writes?


In reply to bbensonk:

This should be possible. But I believe it is useless. You do not know what you are reading via backdoor.

In reply to chr_sue:

Not sure what you mean, so maybe this needs more context.

In our bench, for each register field with a corresponding DUT memory element we do a setup call like this.

reg.add_hdl_path_slice(.name(“DUT_reg_name”), .offset(bit_num), .size(1));

When we do a field.peek() call to the corresponding register field we are able to see the value which corresponds to that memory element in the waves. This allows us to write a sequence which does a field.write() front-door access. Then a loop polls with field.peek() to verify that the field asserts afterwards and that the DUT subsequently cleared it. That is working code.

The problem is our new DUT has an indirect register access. We changed our register adapter to work properly, it just takes longer. Now the DUT register memory element asserts and clears before the front-door field.write() even finishes.

That is why we need a back-door peek to work separately from the front-door write. This is a specific register test. The value is verified 0 through peek before testing this register. If a fork is used the polling loop can begin at the same time as the front-door write. So there’s no chance of missing the DUT memory element assertion.

It would be helpful if you have any ideas on how it might be possible. Thanks.

In reply to bbensonk:

I believe it is quite easy. You are starting a frontdoor . This will modify the content of your registers. Doing a backdoor peek in parallel shows you thhe old or the updated value. You cannot control this.