Using SystemVerilog Clocking Block to verify a simple valid/ready handshaking design

SystemVerilog
,
4

The link is
bitwise or logical operato.

  1. - You have

    verilog task ar_check; begin // <--- NOT NEEDED, delete @(ar_intf_inst.cb_axil_slv); ... endtask // You fire the task in an initial with repeat (3) ar_check;

    Though it is syntactically correct, you may eventually migrate to UVM where tasks are automatic because they are in a class, and in a driver, a task have a purpose or a job to do, as specified by an instruction. The task may also identify an outcome. Consider this example (a counter):

    verilog // in a package, I have a typedef for the type of stuff I want to expose my counter to typedef enum {CT_LOAD, CT_RESET, CT_WAIT, CT_DONE} ct_scen_e; // The transaction, the job with details class counter_xactn extends uvm_sequence_item; rand logic[3:0] data=0; logic[3:0] data_collected, data_viewed; rand logic ld=0, rst_n; rand int reset_cycles, idle_cycles=1; rand int xx; rand ct_scen_e kind; ... enclass // The start of of the driving machine, like opening the store task get_and_drive(); // portion of the code shown here counter_xactn t; // to hold gotten item as a copy, keeping original pristine // do a create (like a new of t forever begin //wait(vif.reset==0); //block until reset released seq_item_port.get_next_item(req); // New item (or job) at every call, send_to_dut(t); // The actual job to do ... seq_item_port.put_response(rsp); // put the response (e.g., here is data) seq_item_port.item_done(); end endtask : get_and_drive // the job task send_to_dut(input counter_xactn item); uvm_report_info(tID,$psprintf("%s : item sent is %0s",tID,item.sprint()),UVM_MEDIUM); copy_items(item_copy, item); // Do this for viewing in waveform view this.vif.driver_cb.kind_cp<=item.kind; // put into interface for debug case(item.kind) CT_LOAD : begin this.load_task(item.data); end CT_RESET : begin this.reset_task(1, item); end CT_WAIT : begin this.idle_task(item.data); end CT_DONE : begin this.done_task(item); end endcase endtask : send_to_dut // more details task load_task(int data); this.vif.driver_cb.data_in <= data; this.vif.driver_cb.rst_n <= 1'b1; this.vif.driver_cb.ld <= 1'b1; @(this.vif.driver_cb)this.vif.driver_cb.ld <= 1'b0; endtask : load_task

    - The point here is that by being more hierarchical, you attack the problem from a top-down viewpoint – stating the engine, feeding the stuff to do (reset, a load, a count, …), sending the details on what a load or a count is to separate tasks. You can do all of that without UVM, until you learn UVM (if you need to).
    - Recommendations:

    verilog // Add in the interface something like typedef enum {INIT, DO,RESULT} scen_e; // << scen_e kind; // << // You may want to use classes, but that is not necessary. // Put your task ar_check in your interface // Use hierarchy as described above.


  2. What I said above sounds overkill, and it is for this model. However, consider it for a more complex model.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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    Real Chip Design and Verification Using Verilog and VHDL($3) Amazon.com
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