Question: Operators in Assertions

SystemVerilog
1

Hi All,

Can anybody tell me which operator I should use in System Verilog assertions, Logical or Bitwise…and Why ??

2

It should be the logical because

  1. that is the intent, it reads better,
  2. Does what you want.
    For example:
    bit[2:0] a=3’b101, b=3’b010;
    bit x, y;
    if(!a) …// Since a >0, !a is false
    if(~a) …// ~a==010, thus ~a is true, not the intent.
    a && b |-> … // a is true, b is true since they are > 1
    // thus a && b is true
    a & b |-> // bitwise and, thus a & b is 3’b000
    // a & b is false
    Ben Cohen SystemVerilog.us
3

In reply to ben@SystemVerilog.us:

It should be what the intent requires. In general, I would stick with logical operators and only use bitwise on vectors greater than 1-bit wide AND the operation requires it, like masking.