Using SystemVerilog Clocking Block to verify a simple valid/ready handshaking design

SystemVerilog
,
2

In reply to markylew:
Some comments (not in any specific order)

  • You tend to use the bitwise instead of the logical operator
    Question: Operators in Assertions | Verification Academy
  • Your use of assertions inside the interface is good.
  • clocking block usage is OK too.
  • I particularly (my preference) don’t like too many begin … end keywords unless absolutely necessary. Specificaly, if the if else statement is of one term, why do you need the begin end?. Also, if you do use lots of begin end, label them

// instead of
always @( posedge aclk )
begin
if ( areset )
arready <= 1'b1;
else begin
if(!arrdy_high_en) begin
if (~arready && arvalid)
arready <= 1'b1;
else
arready <= 1'b0;
end
else begin
// Below have arready high
if (arready && arvalid)
arready <= 1'b0;
else
arready <= 1'b1;
end
end
end
// simplify to
always @( posedge aclk ) begin : alwy1
if (areset)  arready <= 1'b1;
else
if(!arrdy_high_en)
if (~arready && arvalid) arready <= 1'b1;
else arready <= 1'b0;
else  // Below have arready high
if (arready && arvalid) arready <= 1'b0;
else arready <= 1'b1;
end : alwy1
//
// BTW, maybe a case statement might be better here?
// The code was hard to follow.
  • Unless absolutely necessary, I prefer constrained-random tests instead of directed tests. For example, the template I generally use to test my assertions. I then modify the variables and the statistics.

initial begin
repeat(200) begin
@(posedge clk);
if (!randomize(a, b)  with
{ a dist {1'b1:=1, 1'b0:=1};
b dist {1'b1:=1, 1'b0:=2};
}) `uvm_error("MYERR", "This is a randomize error");
end
$finish;
end

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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