using system verilog que can we implement fifo?
In reply to lalithjithan:
Below is a model from my SVA Handbook 4th Edition
// Data queue for verification.
// Queue, maximum size is 2**BIT_DEPTH
word_t dataQ [$:2**BIT_DEPTH-1];
// Data read from queue
word_t data_fromQ;
// Push and Pop tasks
task pop_task;
begin
data_in <= 'X; // unsized Xs
pop <= 1'b1;
data_fromQ <= dataQ.pop_front();
@ (posedge clk);
end
endtask : pop_task
task push_task (word_t data);
begin
$display ("%0t %m Push data %0h ", $time, data);
data_in <= data; //data to be written
push <= 1'b1;
dataQ.push_back(data); // push to dataQ
@ (posedge clk);
end
endtask : push_task
task idle_task(int num_idle_cyles);
begin
push <= 1’b0;
pop <= 1’b0;
data_in <= ‘X;
assert (num_idle_cycles < 10000) else
$warning (“%0t %0m idle_task is invoked with LARGE number of idle cycles %0d “,
num_idle_cycles);
repeat (num_idle_cycles) @ (posedge clk);
end
endtask : idle_task
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
In reply to ben@SystemVerilog.us:
In 2012 systemverilog LRM, there is an example for FIFO and Stack as below in 8.26 interface class chapter.
interface class PutImp#(type PUT_T = logic);
pure virtual function void put(PUT_T a);
endclass
interface class GetImp#(type GET_T = logic);
pure virtual function GET_T get();
endclass
class Fifo#(type T = logic, int DEPTH=1) implements PutImp#(T), GetImp#(T);
T myFifo [$:DEPTH-1];
virtual function void put(T a);
myFifo.push_back(a);
endfunction
virtual function T get();
get = myFifo.pop_front();
endfunction
endclass
class Stack#(type T = logic, int DEPTH=1) implements PutImp#(T), GetImp#(T);
T myFifo [$:DEPTH-1];
virtual function void put(T a);
myFifo.push_front(a);
endfunction
virtual function T get();
get = myFifo.pop_front();
endfunction
endclass
Thankyou Ben & Lina