Using system verilog que can we implement fifo?

SystemVerilog
2

In reply to lalithjithan:
Below is a model from my SVA Handbook 4th Edition


// Data queue for verification.
// Queue, maximum size is 2**BIT_DEPTH
word_t dataQ [$:2**BIT_DEPTH-1];
// Data read from queue
word_t data_fromQ;
// Push and Pop tasks
task pop_task;
  begin
    data_in <= 'X; // unsized Xs
    pop <= 1'b1;
    data_fromQ <= dataQ.pop_front();
    @ (posedge clk);
  end
endtask : pop_task
task push_task (word_t data);
  begin
    $display ("%0t %m Push data %0h ", $time, data);
    data_in <= data; //data to be written
    push <= 1'b1;
    dataQ.push_back(data); // push to dataQ
    @ (posedge clk);
  end
endtask : push_task
task idle_task(int num_idle_cyles);
  begin
    push <= 1’b0;
    pop <= 1’b0;
    data_in <= ‘X;
    assert (num_idle_cycles < 10000) else
     $warning (“%0t %0m idle_task is invoked with LARGE number of idle cycles %0d “, 
        num_idle_cycles);
    repeat (num_idle_cycles) @ (posedge clk);
  end
endtask : idle_task

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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