Use of verilog module signals inside interface

UVM
1

Hi,

I have created one wrapper file where I have instantiated a verilog module and in that module there is noe modport declaration of AXI interface in the port list. So, now I need to connect these interface signals with DUT instantiated inside TB. But those DUT Related signals are already being connected to some other AXI Interface. So, I have been provided with a task where I need to create axi_tap_if.sv file where we will some tasks(subroutines) inside which we will take our Verilog module interface signals and then these tasks will be called from some other file from where these values can be sent to AXI UVC Driver that is already connected in TB with DUT. So, my query is how can I take Verilog module signals inside interface?

2

In reply to Abhijeet Anand:

Could you please show the relevant code?

3

In reply to Abhijeet Anand:

Hello, just so we are clear let me just resume your problem:

  1. You have a DUT already connected to AXI interfaces in your TB module

  2. You have coded up your own new interface which will basically provide some tasks used in the Driver or other UVC components that might need it.

You query is how can I hook up those signals again since already connected to other interfaces?

There could be few ways if i got it properly:

  1. You can create anyway you own interface and connect the input signals to an or gate. You arr gonna or the 2 interface signals the AXI existing one and the new one.

  2. For the output is just a matter of having 2 monitor and 1 driver approach. Basically hook up the signals in your interface to the ones in the AXI interface.

Now while monitoring them it will be fine since the driver is your DUT. Drivings will be fine since you are not creating any double driver.

Another approach is to create an additional layer in the hier like:

Your interface -> AXI interface

Meaning that basically you need to wrap up your interfaces in the new one and use the dot notation to access them all.

Let me know if i got it properly

4

The general approach is you write your axi_tap_if.sv file with all your axi signals as ports of that interface.


interface axi_tap_if#(parameters you need) ( list of all axi ports);
  //your tasks whatever you want to do with these axi signals...
endinterface

You can bind this axi_tap_if at any hierarchy of instance.


module tb;
  //your normal axi signals..
  dut u_dut(axi signals...);
  //you can bind your axi_tap_if here
  bind u_dut axi_tap_if#(...parameter values...) inst_name (signal connections);
  //If you have any other axi you need to tap deep inside dut, you can do that too.
  bind u_dut.hier1.hier2 axi_tap_if#(... parameter values...) inst_name (signal connections);
endmodule