Hi
recently I have seen sequence is used inside clocking block.
What is the use of that? How to apply it for development?
clocking sck @(posedge pclk);
input paddr, psel, penable, pwrite, pwdata;
output prdata;
sequence at_posedge;
1;
endsequence : at_posedge
endclocking: sck
Thanks
AnantharajTV
The only possible advantage of declaring sequences and properties in clocking blocks is the sampling time. Specifically,
If a variable is an input variable of a clocking block, the variable shall be sampled by the clocking block with #1step sampling. Any other type of sampling for the clocking block variable shall result in an error. The sampled value of a such variable is the sampled value produced by the clocking block.
I don’t recommend declaring sequences or properties in clocking blocks; most users don’t, as it complicates things and readability. BTW, you cannot have assertion statements in clocking blocks.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115