Use bit slice in force syntax

SystemVerilog
,
1

force `TOP.llp_nxt[((i+1)*64) -1) -: 63] = val;

Error Message :
[IFRLHS-SELNONCONST] : Illegal force/release used on LHS

Can you please suggest me solution for this issue ?

2

In reply to Niyati Gandhi:

case(i)
0: force `TOP.llp_nxt[((0+1)*64) -1) -: 63] = val;
1: force `TOP.llp_nxt[((1+1)*64) -1) -: 63] = val;
2: force `TOP.llp_nxt[((2+1)*64) -1) -: 63] = val;
3: force `TOP.llp_nxt[((3+1)*64) -1) -: 63] = val;
endcase
3

In reply to dave_59:

Appreciate your last reply

It gives same error as
Error Message :
[IFRLHS-SELNONCONST] : Illegal force/release used on LHS

Bit select or part select must be constant

I am using VCS simulator

Do you have any other solution for it ?

4

In reply to dave_59:

case(i)
0: force TOP.llp_nxt[((0+1)*64) -1) -: 63] = val; 1: force TOP.llp_nxt[((1+1)*64) -1) -: 63] = val;
2: force TOP.llp_nxt[((2+1)*64) -1) -: 63] = val; 3: force TOP.llp_nxt[((3+1)*64) -1) -: 63] = val;
endcase

Issue in detail :

llp_nxt is some signal of RTL.
Now I have 2 RTL

  1. In one RTL ll_nxt length is 256 bits so all 4 case statement as above is valid
  2. In another RTL llp_nxt length is 128 bits so only 2 case [0,1] is valid for that RTL.
    Now I don’t want to put ifdef for RTL so I make sure generation of “i” [case variable] is in limit as per RTL.
    But I want to keep all 4 case statement as it.
    Do you have any solution for the same?

I have tried bit slice which not works for force statement

On case also where RTL has 128bits length for llp_nxt as that time it’s gives error :
[IFRLHS-SELNONCONST] : Illegal force/release used on LHS
Force / release on bit select or part select of vector variable is not valid