Use bit slice in force syntax

SystemVerilog
,
2

In reply to Niyati Gandhi:

case(i)
0: force `TOP.llp_nxt[((0+1)*64) -1) -: 63] = val;
1: force `TOP.llp_nxt[((1+1)*64) -1) -: 63] = val;
2: force `TOP.llp_nxt[((2+1)*64) -1) -: 63] = val;
3: force `TOP.llp_nxt[((3+1)*64) -1) -: 63] = val;
endcase