Unsigned integer with eight implied decimal places

SystemVerilog
1

I want to generate a random 64 bit number which is something like this,

Little-Endian encoded 64 bit unsigned integer with eight implied decimal places

If I use

rand [63:0] abc;

what will be my constraint to restrict legal values?

2

In reply to vg_ql:
you can not use rand without specifiying data type.


 
 rand bit[63:0] abc ; // unsigned 64 bit value

Can you please explain more about your legal constraint range ?

3

In reply to vg_ql:
SystemVerilog only has the capability to generate random integers. So you might have to generate a 64-bit integer and divide it by 108. But representing a fixed point number in a language that only supports integer and real types is another topic.

4

Thank you Dave.

In reply to dave_59: