In reply to ben@SystemVerilog.us:
For : seq1 |-> ##[dyn1:dyn2] seq2; // where dyn1 = 0 , dyn2 = 1
The new code doesn’t evaluate seq2 for 2nd time at time:15 since expression (vdiff>0) is false for ( vdiff > 0 , vdiff-- )[*2:$]
So a solution would be to manually evaluate ‘seq2’ at next clock only if vdiff is 0 after decrement operation i.e LHS sequence of ‘or’ operator should be :
( (vdiff>0, vdiff=vdiff - 1 )[*1:$] ##0( sq or ( (vdiff == 0) ##1 sq ) ) )
For dyn1 = 0 and dyn2 = 1 , seq2 must be evaluated twice. Once after dynamic_delay(0) matches and for 2nd time at next clock after that.
Using the new code ‘vdiff’ is decremented to 0 at same clock that dynamic_delay(0) matches.
Due to repetition range[*1:$] at next clock (vdiff>0) would be false.
With the additional logic ‘seq2’ is evaluated at next clock only if vdiff is 0 for current iteration
I tested the same for 11 scenarios : https://www.edaplayground.com/x/NY55
The code works as per expectations !!