Unexpected results for Dynamic delay range

SystemVerilog
,
8

In reply to ben@SystemVerilog.us:

Ben,
The new code has a limitation when subsequent seq. matches after ##dyn2 clocks
On trying following stimulus :


initial begin  
   $dumpfile("dump.vcd"); $dumpvars;
   d1 = 0 ; d2 = 1 ;    
   #4 ; siga_ = 0; 
   #10 ; data1 = 0 ; data2 = 0;  // ( data1 == data2 ) at time:15
   #82; $finish(); 
  end

The expectation is assertion pass at time:15 however the assertion fails at time:15