In reply to ben@SystemVerilog.us:
One possible solution which works as per intention ( for 6 scenarios that I tested ) : edalink
However the code has a limitation ( lack of sufficient clock ticks for RHS of ‘within’ to match ) as observed for +define+M7.
For +define+M7 even if there are sufficient clock ticks the assertion passes at time:55 instead of the expectation at time:35.
Using ‘within’ in consequent the code only works if I write RHS sequence of ‘within’ as 1[*(dyn1+1):(dyn2+1)] ( Tested for all 7 scenarios )
Now the challenge is to code RHS sequence which is dynamic repeat range: 1[*(dyn1+1):(dyn2+1)]
Any alternate solution possible ?