In reply to ben@SystemVerilog.us:
Ben ,
I believe the expression ( vdiff >= 0 ) is required for scenarios where dyn1 == dyn2.
Due to (vdiff >= 0) the subsequent sequence is evaluated at same time as dynamic_delay(dyn1) completes.
In your edalink using ( vdiff>0 ), if I were to provide stimulus as :
initial begin
d1 = 0 ; d2 = 0 ;
#4 ; siga_ = 0; data1 = 0 ; data2 = 0;
#82; $finish();
end
Instead of assertion pass at T:5 the assertion fails due to (vdiff>0) being false
Whereas if we use (vdiff>=0) the assertion passes at T:5 as per expectations