In reply to ben@SystemVerilog.us:
Hi Ben,
Thanks for inputs. I have looked that up, with accept_on/reject_on we can manipulate the assertion result. That should do.
Lets say for a moment, the off/on (accept/reject) behavior is a dont care.
In that case we just simply assert a concurrent property (it has to be made concurrent because we want it to consume time since we used throughout)inside a clocked always block.
My goal is to rewrite that concurrent assertion with an equivalent task (as tasks can also consume time).Any suggestions on how to do this would be great.
Thanks for the help in advance.