To restrict the visibility of interface to agent only using config_db

UVM
,
1

I want to restrict the accessibility of the interface to the agent component only.
I have used the get method to access the interface inside the test class but it is giving me the shown error.

below is the code where the set method is called.


`include "extended_uvm_test.sv"
`include "interface.sv"
module tb;
  
  logic clk;
  
  always #1 clk=~clk;

  //---------------------------------------
  //interface instance
  //---------------------------------------
  intf intf_h(clk);
  
  initial
    begin
      clk=0;
      #50 $finish;
    end

  //---------------------------------------
  //passing the interface handle to lower heirarchy using set method 
  //---------------------------------------
  initial
    begin
      uvm_config_db#(virtual intf)::set(null,"*.agent_h","intf_h",intf_h); // I have tried with uvm_root::get() also,but no change.
    end
  
  //----------------------------
  //calling test
  //----------------------------
  initial
    begin
      run_test("extended_uvm_test");
    end
  
endmodule:tb

below is the test code where get method is called(inside build phase).


`include "extended_uvm_env.sv"
class extended_uvm_test extends uvm_test;
  
  //------------------------------------------
  //register class to factory
  //------------------------------------------
  `uvm_component_utils(extended_uvm_test);
  
  //---------------------------------------
  //interface instance
  //---------------------------------------  
  virtual intf intf_h;  
  
  //------------------------------------------
  //environment handle instance
  //------------------------------------------
  extended_uvm_env env_h;
  
  //------------------------------------------
  //transactor method
  //------------------------------------------
  function new(string name="dextended_uvm_test", uvm_component parent=null);
    super.new(name, parent);
  endfunction
  
  //------------------------------------------
  //build phase
  //------------------------------------------
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    //create the environment
    env_h=extended_uvm_env::type_id::create("env_h",this);
    if(!uvm_config_db#(virtual intf)::get(this,"","intf_h",intf_h))
      begin
        `uvm_fatal("NO_VIF",{"virtual interface must be set for: ",get_full_name(),".vif"});
      end    
    `uvm_info(get_type_name(),$sformatf("\t TEST::BUILD_PHASE time=%0t",$time),UVM_LOW);
  endfunction:build_phase
  
  //------------------------------------------------
  //connect phase
  //------------------------------------------------
  function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    `uvm_info(get_type_name(),$sformatf("\t TEST::CONNECT_PHASE time=%0t",$time),UVM_LOW);
  endfunction:connect_phase

  //------------------------------------------------
  //run phase
  //------------------------------------------------
  virtual task run_phase(uvm_phase phase);
    super.run_phase(phase);
    phase.raise_objection(this);
    @(posedge intf_h.clk);
    run_display();
    phase.drop_objection(this);
  endtask:run_phase
  
  //------------------------------------------------
  //display the comment 
  //------------------------------------------------
  virtual task run_display();
    
    @(posedge intf_h.clk);
    
    `uvm_info(get_type_name(),$sformatf("\t MONITOR::RUN_PHASE time=%0t",$time),UVM_LOW);
  endtask:run_display  
  
  
endclass:extended_uvm_test

I am getting the following error.


UVM_FATAL extended_uvm_test.sv(35) @ 0: uvm_test_top [NO_VIF] virtual interface must be set for: uvm_test_top.vif

what could be the issue? i guess, it is due to the execution time.
please help me out.

Thanks & Regards
jj_bukhari

2

In reply to jj_bukhari:

Your problem is in the config_db set command:

uvm_config_db#(virtual intf)::set(null,"*.agent_h","intf_h",intf_h);

Your code restricts the virtual interface to a component which has at the end of its hierarchical path ‘agent_h’.
Replacing the 2nd argument with awildcard ‘*’ will work.

3

In reply to chr_sue:

Thank you 4 reply,

What should be the 2nd argument if I want to restrict the visibility to test only?

I tried “tb.uvm_test_top” , “.uvm_test_top", “tb.extended_uvm_test”, and ".extended_uvm_test”
but none of these worked.

Thank you.

4

In reply to jj_bukhari:

It depends on your strategy for distributing the virtual interfaces to your environment. The test itself does not need the virtual interface. It is a transaction-level component. Only when you are using a configuration object to distribute the virtual interface through your system you woule do a get in the test component.
uvm_test_top is the implicit instannce name of the test component. If you are using this it is restricted to this component.

5

In reply to chr_sue:

Actually I wanted to get the CLK signal from the interface into the test, that’s why I have used the get method inside the test component.

I got your point about using wildcard “*”. but I want to get the interface handle inside the test component and I am getting error in that.

I hope, I made my concern clear.
waiting for a solution…

Thanks & Regards
jj_bukhari

6

In reply to jj_bukhari:

The test is a TLM model which does not know anything about clock cycles and control signals. Any timing will be controlled by the driverwhich has both interfaces the pinlevel (virtual) interface and a TLM port.
The get/put are blocking commands which are waiting until the next item is needed.

7

In reply to chr_sue:

Thank you chr_sue for patiently clearing my doubt.

I have one confusion that,
why, when I use the wildcard “*” every clocking element is being executed(in all components (test,env, agent, driver, monitor, scoreboard, sequencer) but when I restricted the visibility to test only or environment only then it is giving me an error?

another question is regarding my understanding of the scope given below.
if I write, let’s say, “top.*.agent” in the second argument then the visibility will be in the test, environment, and agent component. correct me if I understood it incorrectly.

Thank you

8

In reply to jj_bukhari:

If you are using as the 2nd argument the wildcard “", then there is no linitation for any component to retrieve the interface from the config_db.
If you are using a pathe like this "top..agent”, then the access is restricted to components with the name ‘agent’, independently how the hierarchical path between top and agent is.

9

In reply to chr_sue:

In reply to jj_bukhari:
If you are using a path like this “top.*.agent”, then the access is restricted to components with the name ‘agent’, independently how the hierarchical path between top and agent is.

but it is not working, sir.

below set method, I have used in my main question above(in test),


uvm_config_db#(virtual intf)::set(null,"*.agent_h","intf_h",intf_h); // I have tried with uvm_root::get() also,but no change.

and below get method, I have used in the test.


uvm_config_db#(virtual intf)::get(this,"","intf_h",intf_h)
10

In reply to jj_bukhari:

That is correct, because the set command does not allow to retrieve intf_h in the test it is only allowed in any component which is called ‘agent_h’ in your UVM hierarchy.