To measure clock with same phase and 180 degree out of phase

UVM
,
1

I want to measure two clock frequency with same phase

property phase_smps_pulse_check;
    realtime t1, t2;
    @(posedge tb_clk) (1, t1=$realtime) ##0 (top_adcdigen && top_adcanaen) |-> @(posedge top_smps_pulse) (1, t2=$realtime) ##0 ((t2-t1) >= (0+1fs));
  endproperty

assert property(phase_smps_pulse_check);

It is giving assertion error. What is wrong in it ?

Also I want to measure 180 degree out phase for two clock , what to change it in the code ?

I have added the stimulii in below link.

wave hosted at ImgBB — ImgBB

2

In reply to kulua:

We have no idea what is wrong with your code because you have not shown the stimulus. Please see your previous question.

Please use code tags making your code easier to read. I have added them for you many times.

3

In reply to dave_59:

I have added the stimulii in below link