To check clock toggling

SystemVerilog
, ,
1

Hi,
What are the different ways to check clock is toggling or not when reset is enabled?
(with and without assertions)

2

In reply to Kishankk:

This link should give you 2 approaches you can take.
https://verificationacademy.com/forums/systemverilog/assertion-implementation#reply-111758

Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

or Links_to_papers_books - Google Docs

3

Thank you so much Ben for the assertion approach and your papers and books link.
Much Useful!!!

Can you provide any other ways to check the clock toggling without assertions?

4

In reply to Kishankk:
That link

provides a solution without SVA.

Hi,
What are the different ways to check clock is toggling or not when reset is enabled?
(with and without assertions)

Using the same concepts as explained in my previous link


// Modified to your requirements that for now are very vague. 
//   If reset==0 then check clock toggling forever. Period of the clk==1/2 T
//   If reset==1 then no toggle  
// 1) Using a task that can be called without a timeout 
   bit err0, err1; // for debug
   let T= 3; // T is a 1/2 period
   let T1= T+1; //T1, a bit more than T to capture a clk edge 
    task automatic t_clk_reset1();
       int count; 
       while(reset==1) begin 
         fork
          #T1; // a bit more than a half period 
          //   If reset==1 then no toggle until reset==1 
          @(posedge clk) if(reset==1) count=count+1; 
           // should not count when reset==1
         join_any
         am_3clk_after_en: assert_final(reset==1 && count==0) else err1=err1+1;
         count=0; 
      end
    endtask

   task automatic t_clk_reset0();
     int count; 
     while(reset==0) begin
       fork
          #T1; // a bit more than a half period 
          //   If reset==0 then check clock toggling .
           @(posedge clk) if(reset==0) count=count+1; // should count
       join_any
       am_3clk_after_en: assert_final(reset==0 && count>0) else err0=err0+1;
       count=0; 
     end
    endtask

    always @(reset)  begin
      t_clk_reset1();
      t_clk_reset0();
    end

Getting started with verification with SystemVerilog

Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

or Links_to_papers_books - Google Docs

5

In reply to ben@SystemVerilog.us:

DId an update above.
This is untested, but it looks OK now.
Tasks are fired upon a change in reset.
Each task forks 2 processes, one is a fixed delay during which a clk event may occur and may update a count.
Any of the processes, timeout or clocking event, conclude the fork and an immediate assertion check the count.
The while repeats the test until a change in the reset, upon which new tasks are fired.

6

In reply to ben@SystemVerilog.us:
TB for the solution if clock toggling or not toggling with reset

Note the firing of the tasks with a fork join_none


module m;
  bit reset, clk, tbclk, a=1, ferror; 
  int err0, err1; // for debug
  always #4 tbclk = !tbclk; // testbench clock 
  always #3 clk = !clk && ferror==0; 
  function void f(bit i);
      if(i==1) err1=err1+1;
      else err0=err0+1;
  endfunction
                    
  task automatic t_clk_reset1();
     int count; 
     while(reset==1) begin 
        fork
          #8; // time to detect a clk posedge 
              //   If reset==1 then no toggle until reset==1 
          @(posedge clk) if(reset==1) count=count+1; 
              // should not count when reset==1
        join_any
        am_3clk_after_en: assert final(reset==0 || count==0) else f(1);
        count=0; 
      end
  endtask
              
  task automatic t_clk_reset0();
     int count; 
    while(reset==0) begin
      fork
        #8; // a bit more than a half period 
            //   If reset==0 then check clock toggling .
        @(posedge clk) if(reset==0) count=count+1; // should count
      join_any
      am_3clk_after_en: assert final(reset==1 || count>0) else f(0);
      count=0; 
    end
  endtask
              
  always @(reset)  begin // tas firing 
    fork 
      t_clk_reset1();
      t_clk_reset0();
    join_none
  end

  initial begin 
    $dumpfile("dump.vcd"); $dumpvars;
    // normal operation
    #1 reset=1; #1;
    reset=0; ferror=0; 
    repeat(5)  @(posedge clk);
    reset=1; 
    #7 fork repeat(5) begin ferror=1; @(posedge clk); end join_none 
    repeat(5) @(posedge tbclk); 
    reset=0; 
    #7 fork repeat(5) begin ferror=1; @(posedge clk); end join_none 
    repeat(9) @(posedge tbclk); 
    ferror=0; 
    reset=0;     #30 $finish;
  end
endmodule