In reply to Kishankk:
That link
provides a solution without SVA.
Hi,
What are the different ways to check clock is toggling or not when reset is enabled?
(with and without assertions)
Using the same concepts as explained in my previous link
// Modified to your requirements that for now are very vague.
// If reset==0 then check clock toggling forever. Period of the clk==1/2 T
// If reset==1 then no toggle
// 1) Using a task that can be called without a timeout
bit err0, err1; // for debug
let T= 3; // T is a 1/2 period
let T1= T+1; //T1, a bit more than T to capture a clk edge
task automatic t_clk_reset1();
int count;
while(reset==1) begin
fork
#T1; // a bit more than a half period
// If reset==1 then no toggle until reset==1
@(posedge clk) if(reset==1) count=count+1;
// should not count when reset==1
join_any
am_3clk_after_en: assert_final(reset==1 && count==0) else err1=err1+1;
count=0;
end
endtask
task automatic t_clk_reset0();
int count;
while(reset==0) begin
fork
#T1; // a bit more than a half period
// If reset==0 then check clock toggling .
@(posedge clk) if(reset==0) count=count+1; // should count
join_any
am_3clk_after_en: assert_final(reset==0 && count>0) else err0=err0+1;
count=0;
end
endtask
always @(reset) begin
t_clk_reset1();
t_clk_reset0();
end
Getting started with verification with SystemVerilog
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.