Hi all,
I’m trying to use the tlm fifo shifter register to implement a delay (like a shifter register);
in my example I’d like to have a 10 clk tick delay. What I see is that the delay works only for first 10 clock ticks.
Have anybode also tried this way? I can’t find my issue :(
Here is my code
traffic_passive_item trans_collected, trans_collected_delay;
uvm_analysis_port #(traffic_passive_item) analysis_loop_port;
uvm_tlm_analysis_fifo #(traffic_passive_item) traffic_buffer_fifo;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase (phase);
trans_collected = traffic_passive_item::type_id::create("trans_collected");
trans_collected_delay = traffic_passive_item::type_id::create("trans_collected_delay");
analysis_loop_port = new("analysis_loop_port", this);
traffic_buffer_fifo = new ("traffic_buffer_fifo", this);
endfunction: build_phase
forever begin
fork
get_vif_signals();
buffer_data();
send_data_to_mbox();
join_any
end
task buffer_data();
@(posedge vif.clk);
if(vif.en_ck) begin
if(vif.data_en) begin
traffic_buffer_fifo.try_put(trans_collected);
end
end
else
wr_en_debug = 1'b0;
endtask
task send_data_to_mbox();
@(posedge vif.clk);
if (vif.reset_n == 1'b0) begin
fifo_level = 0;
end
else begin
if(vif.en_ck) begin
fifo_level = traffic_buffer_fifo.used();
if(fifo_level > 10) begin
trans_collected_delay = new();
traffic_buffer_fifo.try_get(trans_collected_delay);
analysis_loop_port.write(trans_collected_delay);
end
end
end
endtask
task get_vif_signals();
@(posedge vif.clk);
data_dut_out_1 = vif.data_1;
data_dut_out_2 = vif.data_2;
trans_collected = new();
trans_collected.data_1 = vif.data_1;
trans_collected.data_2 = vif.data_2;
endtask
thanks to all