The use of get_randstate() and set_randstate()

UVM
,
1

Hi, What’s the use of get_randstate() and set_randstate() in the following code?

  function void free();
	   process p;
	   string s;

..............
   p = process::self();
      if(p != null)
      	s = p.get_randstate();
      m_cfg_dap = new("cfg_dap");
      if(p != null)
      	p.set_randstate(s)


  endfunction
2

It’s used to ensure random stability in the current process(thread). A RNG is used up for each class constructed by the current thread. By wrapping the the construction of m_cfg_dap around a set/get, you are protecting the random stability of the thread calling the function free. It usually used when inserting debug code so the construction of extra class object does not disturb the code that follows it. Whether it’s really needed here is hard to know without seeing more code.

3

In reply to dave_59:

Hi Dave,
thanks for your quick answer,I have another question,SystemVerilog has eight name spaces for identifiers,I have read the 3.13 chapter of systemverilog 1800 standard ,I find it hard to comprehend Name spaces ，and also The standard does not give some examples,have you some papers about it ?

4

In reply to wszhong631:

In the future, please post a new question under a different topic. It makes it easier for people with similar questions to search.

As far as your question is concerned, it would help if you first assumed there was only one namespace. It becomes confusing when you use the same name to represent different things. But that becomes difficult in practice on a large project with multiple collaborators. So you need to understand these namespaces to prevent conflicts and understand how the compiler will attempt to resolve them.

The easiest namespace to describe is the text macro namespace. That’s because a macro name always has a backtick (`) in front of it and could never be confused with the name of anything else.

The best way to understand the other namespaces is understand the constructs they refer to. For example here is a good description of SV packages. http://openesl.org/systemverilog-wiki/Dissecting_SystemVerilog_Packages