Test environment architecture

UVM
1

Hi,
I’m completely new to UVM and I’d like to consult on the architecture of test environment

I have an simple FPGA with:

  • Interface to the CPU host
  • A few peripherals with its own registers, hooked to the CPU bus and Interfaces to external world.
  • Those peripherals do communicate with each other internally

I will create UVC for each interface. I have a few questions as follow:
Q1) a) Should I have a central register model at the top and all UVCs will reference to this model?
b) OR should each UVC have its own register model?
With b) it’s easier to bring the UVC from project to project but because the peripherals do communicate with each other, this makes things really messy.

Q2) a) For scoreboard, should I have a central scoreboard that recieves transactions from all UVC then perform checks (most examples/books do it this way)?
b) OR should I create a checker inside each UVC and perform checks internally. For example, the SPI slave UVC would have to monitor 2 interfaces: the CPU interface and the SPI interface to check if the SPI frames are generated correctly.

In summary:

  • Where should we put the register model, Central at top or inside UVC?
  • How to deal with the case where peripherals are communicating with each other. What kind of ports should be used at each UVC to facilitate this?
  • Where should we put the checker, central at top or inside each UVC?

Thank you!

Jeff

2

Register model is orthogonal to the UVC or testbench structure, infact they are more like data transactions. It follows the design block-level hierarchy. As you go from block to chip the model stays the same but the address map might change. This helps in reusing the register references in sequences or scoreboards as you reuse the testbench structure from block to chip.

Peripherals communicating to each other can be done in multiple ways based on the test. It can be part of configuration database or it can be something that gets represented on the DUT interface that one can then query from.

Each UVC has a monitor dedicated to one interface (in your case SPI slave interface is collection of CPU interface and SPI signals). Depending on the level you are testing at you will use different scoreboards which typically read the monitored results from two or more UVCs.

I might have confused you with the answers. But if you are new to all this I would highly recommend going through some of the tutorials on the verification academy to get the architecting right. Then build the testbench one UVC at a time, incrementally. Good luck.

3

In reply to sk_verifier:

Thanks for the info.
I think I roughly understand what you mean.
I might have misundertood the role of UVC. UVC shouldn’t be related to register model of the SOC.
I’ll build the tb with UVCs and without the register model first.