Register model is orthogonal to the UVC or testbench structure, infact they are more like data transactions. It follows the design block-level hierarchy. As you go from block to chip the model stays the same but the address map might change. This helps in reusing the register references in sequences or scoreboards as you reuse the testbench structure from block to chip.
Peripherals communicating to each other can be done in multiple ways based on the test. It can be part of configuration database or it can be something that gets represented on the DUT interface that one can then query from.
Each UVC has a monitor dedicated to one interface (in your case SPI slave interface is collection of CPU interface and SPI signals). Depending on the level you are testing at you will use different scoreboards which typically read the monitored results from two or more UVCs.
I might have confused you with the answers. But if you are new to all this I would highly recommend going through some of the tutorials on the verification academy to get the architecting right. Then build the testbench one UVC at a time, incrementally. Good luck.