Test case of simple UVM environment is running infinite

UVM
1

Hello Forum,

I have designed the simple rtl of four bit full adder. To verify this, i have created the very simple
UVM environment. I need help in knowing the reason of infinite running of test case. I have checked the
environment but something is missing.

2

In reply to sunils:

If you do not show more about your environment it is near impossible to give you an advice.

3

In reply to chr_sue:

Hi Chr,

I am not sure which file, i need to show you. The environment is very basic and contains
driver, sequencer, monitor, transaction, two subscriber and driver, agent, environment and two configuration file for agent and environment and testcase.

4

In reply to sunils:

I’ll try to ask more specifically …
What do you mean with it is running infintely.
Does it always create new seq_items/Transactions on the driving side or is only the clock still running?

5

In reply to chr_sue:

Hello Sue,

I am just verifying the four bit full adder/subtractor using the uvm environment. It doesn’t contain the clock. Now it is printing the below message endlessly:

UVM_INFO scoreboard.sv(25) @ 0: uvm_test_top.env.sbds [scoreboard] Input are Equals.
# ------------------------------
# Name    Type      Size  Value 
# ------------------------------
# tm      trans     -     @24715
#   in1   integral  4     'h0   
#   in2   integral  4     'h0   
#   ctrl  integral  1     'h0   
#   out   integral  4     'h0   
# ------------------------------

However, i am trying to randomize the inputs in1 and in2 ctrl is one bit signal and the output. But it is giving nothing but above that too endlessly.

6

In reply to sunils:

You should use a clock Signal to get some progress in time. If you do not your environment stays a time 0.
You are showing the print of a transaction from the scoreboard, but you do not show where this transaction comes from. Before looking to the scoreboard you should look to the driver and investigate which transacions are arriving here.

7

In reply to chr_sue:

Hello Chr,
The clock is implemented. But now the test case is not progressing. It stucks at:

UVM_INFO @ 0: reporter [RNTST] Running test test_pos...

Could you please help in this regard.

8

In reply to sunils:

Hello,

I am not sure about the question. but Please check in testcase runphase. If you raise the objection,then objection must be dropped.

If you do not dropped the raised objection in testcase. Simulation will Run Infinite Time

Thanks,
Mitesh Patel