Test case of simple UVM environment is running infinite

UVM
5

In reply to chr_sue:

Hello Sue,

I am just verifying the four bit full adder/subtractor using the uvm environment. It doesn’t contain the clock. Now it is printing the below message endlessly:

UVM_INFO scoreboard.sv(25) @ 0: uvm_test_top.env.sbds [scoreboard] Input are Equals.
# ------------------------------
# Name    Type      Size  Value 
# ------------------------------
# tm      trans     -     @24715
#   in1   integral  4     'h0   
#   in2   integral  4     'h0   
#   ctrl  integral  1     'h0   
#   out   integral  4     'h0   
# ------------------------------

However, i am trying to randomize the inputs in1 and in2 ctrl is one bit signal and the output. But it is giving nothing but above that too endlessly.