Task in systemverilog

In reply to sbellock:

. thank you for your valuable, i am trying to implement using following code, but failing to synthesize in task.

cnt=0;
always @(posedge clk)
cnt=cnt+1;

del=cnt[20];

and using
repeat(10)@(posedge clk)
x=1;

Please help me to solve this, i need to implement this functionality in task as I require it many times. in module it works fine , but not in task. kindly help me