Task in systemverilog

SystemVerilog
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In reply to svkatwe:

What you’ve written is a behavioral model of an SRAM interface, which is fine for simulation, but it cannot be synthesized. So code like

#1 assign CLE=1;
#1 assign RD_N=1;
#1 assign ALE_N=1;
#1 assign CS_N =1;
#1 assign WR_N=1;

needs to be replaced with synthesizable counters.