Sytem Verilog port 'actual interface error'

SystemVerilog
1

I have constructed a simple System verlog module and a test-bench for calculating the value of nCr for different combinations of n and r. For this i have connected the DUT and the testbench by constructing a simple modport interface ‘combinter’. The ‘top’ module is also constructed. Below is the actual code for my module, testbench, interface and top module:

interface: int.svh

interface combinter();
  logic [6:0] n;
  logic [1:0] r;
  logic [12:0] C;
  
  modport DUT(input n,r, output C);
  modport TEST(output n,r,input C);
endinterface: combinter

module: combin.sv

`timescale 1ns / 1ps

///Verilog module for calculating nCr, where n is a 7 bit//
///integer and r= 0,1,2//
///author: Rohan Pandit//
 
module combin(combinter.DUT combif);
//input [6:0] n,     // inputs n and r//
//input [1:0] r,
//output reg [12:0] C  //output C//


always @(combif.n or combif.r) //enter the loop only when n or r changes//
   begin
	if (combif.n < combif.r) 
	begin
	combif.C = 13'd0;
	end
   else if(combif.r == 2'b00 && combif.n >= combif.r)  // case 1 : r=0//
        begin
         combif.C = 13'd1;
        end
     else if(combif.r == 2'b01 && combif.n >= combif.r) // case 2: r=1//
        begin	
        combif.C = combif.n;
        end
     else if(combif.r == 2'b10 && combif.n >= combif.r) // case 3: r=2//
        begin
           case(combif.n)
 7'd2: combif.C =   13'd1;
 7'd3: combif.C =   13'd3;
 7'd4: combif.C =   13'd6;
 7'd5: combif.C =   13'd10;
 7'd6: combif.C =   13'd15;
 7'd7: combif.C =   13'd21;
 7'd8: combif.C =   13'd28;
 7'd9: combif.C =   13'd36;
 7'd10: combif.C =   13'd45;
 7'd11: combif.C =   13'd55;
 7'd12: combif.C =   13'd66;
 7'd13: combif.C =   13'd78;
 7'd14: combif.C =   13'd91;
 7'd15: combif.C =   13'd105;
 7'd16: combif.C =   13'd120;
 7'd17: combif.C =   13'd136;
 7'd18: combif.C =   13'd153;
 7'd19: combif.C =   13'd171;
 7'd20: combif.C =   13'd190;
 7'd21: combif.C =   13'd210;
 7'd22: combif.C =   13'd231;
 7'd23: combif.C =   13'd253;
 7'd24: combif.C =   13'd276;
 7'd25: combif.C =   13'd300;
 7'd26: combif.C =   13'd325;
 7'd27: combif.C =   13'd351;
 7'd28: combif.C =   13'd378;
 7'd29: combif.C =   13'd406;
 7'd30: combif.C =   13'd435;
 7'd31: combif.C =   13'd465;
 7'd32: combif.C =   13'd496;
 7'd33: combif.C =   13'd528;
 7'd34: combif.C =   13'd561;
 7'd35: combif.C =   13'd595;
 7'd36: combif.C =   13'd630;
 7'd37: combif.C =   13'd666;
 7'd38: combif.C =   13'd703;
 7'd39: combif.C =   13'd741;
 7'd40: combif.C =   13'd780;
 7'd41: combif.C =   13'd820;
 7'd42: combif.C =   13'd861;
 7'd43: combif.C =   13'd903;
 7'd44: combif.C =   13'd946;
 7'd45: combif.C =   13'd990;
 7'd46: combif.C =   13'd1035;
 7'd47: combif.C =   13'd1081;
 7'd48: combif.C =   13'd1128;
 7'd49: combif.C =   13'd1176;
 7'd50: combif.C =   13'd1225;
 7'd51: combif.C =   13'd1275;
 7'd52: combif.C =   13'd1326;
 7'd53: combif.C =   13'd1378;
 7'd54: combif.C =   13'd1431;
 7'd55: combif.C =   13'd1485;
 7'd56: combif.C =   13'd1540;
 7'd57: combif.C =   13'd1596;
 7'd58: combif.C =   13'd1653;
 7'd59: combif.C =   13'd1711;
 7'd60: combif.C =   13'd1770;
 7'd61: combif.C =   13'd1830;
 7'd62: combif.C =   13'd1891;
 7'd63: combif.C =   13'd1953;
 7'd64: combif.C =   13'd2016;
 7'd65: combif.C =   13'd2080;
 7'd66: combif.C =   13'd2145;
 7'd67: combif.C =   13'd2211;
 7'd68: combif.C =   13'd2278;
 7'd69: combif.C =   13'd2346;
 7'd70: combif.C =   13'd2415;
 7'd71: combif.C =   13'd2485;
 7'd72: combif.C =   13'd2556;
 7'd73: combif.C =   13'd2628;
 7'd74: combif.C =   13'd2701;
 7'd75: combif.C =   13'd2775;
 7'd76: combif.C =   13'd2850;
 7'd77: combif.C =   13'd2926;
 7'd78: combif.C =   13'd3003;
 7'd79: combif.C =   13'd3081;
 7'd80: combif.C =   13'd3160;
 7'd81: combif.C =   13'd3240;
 7'd82: combif.C =   13'd3321;
 7'd83: combif.C =   13'd3403;
 7'd84: combif.C =   13'd3486;
 7'd85: combif.C =   13'd3570;
 7'd86: combif.C =   13'd3655;
 7'd87: combif.C =   13'd3741;
 7'd88: combif.C =   13'd3828;
 7'd89: combif.C =   13'd3916;
 7'd90: combif.C =   13'd4005;
 7'd91: combif.C =   13'd4095;
 7'd92: combif.C =   13'd4186;
 7'd93: combif.C =   13'd4278;
 7'd94: combif.C =   13'd4371;
 7'd95: combif.C =   13'd4465;
 7'd96: combif.C =   13'd4560;
 7'd97: combif.C =   13'd4656;
 7'd98: combif.C =   13'd4753;
 7'd99: combif.C =   13'd4851;
 7'd100: combif.C =   13'd4950;
 7'd101: combif.C =   13'd5050;
 7'd102: combif.C =   13'd5151;
 7'd103: combif.C =   13'd5253;
 7'd104: combif.C =   13'd5356;
 7'd105: combif.C =   13'd5460;
 7'd106: combif.C =   13'd5565;
 7'd107: combif.C =   13'd5671;
 7'd108: combif.C =   13'd5778;
 7'd109: combif.C =   13'd5886;
 7'd110: combif.C =   13'd5995;
 7'd111: combif.C =   13'd6105;
 7'd112: combif.C =   13'd6216;
 7'd113: combif.C =   13'd6328;
 7'd114: combif.C =   13'd6441;
 7'd115: combif.C =   13'd6555;
 7'd116: combif.C =   13'd6670;
 7'd117: combif.C =   13'd6786;
 7'd118: combif.C =   13'd6903;
 7'd119: combif.C =   13'd7021;
 7'd120: combif.C =   13'd7140;
 7'd121: combif.C =   13'd7260;
 7'd122: combif.C =   13'd7381;
 7'd123: combif.C =   13'd7503;
 7'd124: combif.C =   13'd7626;
 7'd125: combif.C =   13'd7750;
 7'd126: combif.C =   13'd7875;
 7'd127: combif.C =   13'd8001;
 
 default: combif.C = 13'dx;
endcase
end

else if ((combif.n > 127) || (combif.r > 2))
	 begin
	 combif.C = 13'bxxxxxxxxxxxxx;
	 end  
    end
endmodule

testbench: combin_tb.sv:

`timescale 1ns / 1ps

module combin_tb (combinter.TEST combif);

  int a,b;
  bit check;
  logic [12:0] C1;

initial
begin
	$display("Module combin(): Engineer Rohan Pandit");
        check = 0;
	combif.r = 2'd0;
	combif.n = 7'd0;
 /* foreach(n[i])
    n[i] = i;
  foreach(r[j])
    n[j] = j;*/
	for (a = 0; a<=2; a = a +1)
	begin
	combif.n = 7'd0;
	for (b = 0; b<=127; b= b+1)
	begin
      if(combif.r == 2'b00)  // case 1: r=0//
        begin
         C1 = 13'd1;
         #2
          if( combif.C !== C1)
          begin
          check = 1;
          #2
            $display("Fail: n = %d, r = %d, out = %d, expected output = %d", combif.n, combif.r, combif.C, C1);
          end
         end
      else if(combif.r == 2'b01) // case 2: r=1//
        begin
          C1 = combif.n;
         #2
          if( combif.C !== C1)
          begin
          check = 1;
          #2
            $display("Fail: n = %d, r = %d, out = %d, expected output = %d", combif.n, combif.r, combif.C, C1);
          end
        end
      else if(combif.r == 2'b10)  // case 3: r=2//
        begin
          C1 = ((combif.n)*((combif.n)-1)) / 2;
          #2
			 if( combif.C !== C1)
          begin
          check = 1;
          #2
            $display("Fail: n = %d, r = %d, out = %d, expected output = %d", combif.n, combif.r, combif.C, C1);
          end
          end			 
	combif.n = combif.n + 1 ;
	end        
	combif.r = combif.r + 1 ;
	end
      if(check != 1)
           $display("Benchmark passed");
      else $display("Benchmark failed");
end

endmodule

interface: int.svh

interface combinter();
  logic [6:0] n;
  logic [1:0] r;
  logic [12:0] C;
  
  modport DUT(input n,r, output C);
  modport TEST(output n,r,input C);
endinterface: combinter

top module: top.sv

module top;
  
  combinter combif();

  combin u1(combif.DUT);
	
  combin_tb t1(combif.TEST);

endmodule

The problem is every time i compile the these modules, they compile perfectly, but while simulating it gives the following error every time:

"(vsim-3695) /u0/users/9/rpandit2/DSD2/msim_tut/tb/combin_tb.sv(0): T he interface port ‘combif’ must be passed an actual interface.

Time: 0 ps Iteration: 0 Instance: /combin_tb File: /u0/users/9/rpandit2/D SD2/msim_tut/tb/combin_tb.sv

FATAL ERROR while loading design

Error loading design

I am stuck at this point even after trying all possible solutions and methods. Please do help and suggest some solutions.

2

In reply to rpandit2:
Works for me. I put every file on the command line. How did you compile it?

3

In reply to dave_59:

Thanks for your speedy reply.

I compiled this in ModelSim SE-64 10.0c edition. I am also able to successfully compile the above codes but i am constantly getting the above simulation error, even after successful compilation. I am working on linux and the commands used for simulation of the test-bench are :

vsim -c sim.combin_tb -do “run -all; exit”
vsim -novopt combin_tb

Please do reply for any suggestions for modifications in the above code, because i probably think there’s something wrong in the syntax for the interface instantiation in the test-bench module : combin_tb.sv, that’s where the simulation error is popping up.

4

In reply to rpandit2:

I tried the following which worked for me.

vsim -voptargs=“+acc” top -do “run -all”

This results in…

run -all

Module combin(): Engineer Rohan Pandit

Benchmark passed

‘top’ is the module to load into the simulator, not ‘combin_tb’
I get the same error as you if I try to load combin_tb

p.s. don’t use -novopt as this disables all optimzations and gives you poor simulation performance. Better to use -voptargs=“+acc” which gives you full visibility of the design internals

5

In reply to graeme_jessiman:

Thanks a lot bro!!! it worked for me now.