Systemverilog shift operator question

SystemVerilog
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3

In reply to dave_59:

Thanks for the push and hint Dave. I tried below code but i am confused on how to shift only odd bits. when we shift a vector all bits will be shifted right?


 bit[7:0] a = 8'b1100_0110 ;
  bit[7:0] b ;  
  initial begin
    for(bit[2:0] idx = 0 ; idx< 7 ; idx=idx+1'b1) begin
      if (idx[0] ) begin 
        b = a << idx ;
        $display("value of b %b",b);
        $display("value of idx %d",idx);
        $display("value of a a[%d] = %b ",idx,a[idx]);
      end
    end