SystemVerilog parameter_declaration syntax

SystemVerilog
,
1

I’m writing a python parser for SystemVerilog (LRM 3.1a) and one of my test cases is a Verilog module that is failing at a “parameter_declatation”. I was under the impression that SV was mostly backward compatible and couldn’t find where this was an exception.

The simple line of code is:

parameter NOTHING=0;

According to the syntax for “parameter_declaration”, a “data_type_or_implicit” is required between “parameter” and “NOTHING” and none of the derived syntax allows it to be optional (ie. blank). Yet I have seen quite a few examples of this syntax including a discussion of how the data type is an implicit integer (for both Verilog and SystemVerilog).

The code compiles fine at edaplayground.com and I don’t have access to one of the big simulators so can’t check it out. It this allowed? Is there some sort of switch required to get it to compile?

Is my interpretation of the specification missing something?

Thanks in advance for any answers.

Regards,
Matt Hsu

2

Found my own answer. In this:

data_type_or_implicit ::= data_type | [ signing ] { packed_dimension }

both the “signing” and “packed_dimension” are optional. My parse problem must be somewhere else.

3

In reply to matt_hsu:

The SystemVerilog 3.1a revision is a defunct standard. You should be using IEEE 1800-2012.