Systemverilog inheritance, how to call multi level up function

SystemVerilog
,
1

I have a test have hierarchy like this:

class test_A;
    virtual function drive();
endclass
class test_B extends test_A;
    virtual function drive();
        super.drive();
        ...
    endfunction
endclass
class test_c extends test_B;
    virtual funciton drive();
endclass

For drive() inside test_c, I want to call drive() inside test_a and then add some code. May I know how can I do so? I cannot directly derive from test_A since other funcitons are same in test_B.

2

In reply to aaaaaa:

You can use the scope operator ::

class test_c extends test_B;
    virtual funciton drive();
       // scope code before
       test_A::drive();
       // some code after
    endfunction 
endclass
3

In reply to aaaaaa:
Thanks Dave.


module top;
  
class test_A;
    virtual function drive();
      $display("IN TEST A");
    endfunction
endclass
class test_B extends test_A;
    virtual function drive();
        super.drive();
      $display("IN TEST B");
    endfunction    
endclass
class test_c extends test_B;
    virtual function drive();
      test_A::drive();
     $display("IN TEST C");
    endfunction  
endclass

 test_c c;
  initial begin
    c=new();
    c.drive();
  end
endmodule