In reply to ianmurph:
The expect statement is a procedural blocking statement that allows waiting on a property evaluation. While the expect statement is not considered SVA because it does not provide any verification significance, but rather a sync capability using properties.
Use the immediate and concurrent assertion statements (I.e., assert, assert property).
Use a good book. In the meantime, definitely read my paper Understanding the SVA Engine,
(Item 3 in my signature). That paper assumes that you know what a task is.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…
- SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
- Free books: * Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
- Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
- A Pragmatic Approach to VMM Adoption
http://SystemVerilog.us/vf/VMM/VMM_pdf_release070506.zip
http://SystemVerilog.us/vf/VMM/VMM_code_release_071806.tar
- Papers:
- Understanding the SVA Engine,
Verification Horizons - July 2020 | Verification Academy - Reflections on Users’ Experiences with SVA
Reflections on Users’ Experiences with SVA | Verification Horizons - March 2022 | Verification Academy - SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/