SystemVerilog constraint implication with multiple variable

SystemVerilog
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3

In reply to Ariel Elliassi:

The right hand side of an implication can be a constraint set:

constraint example {
flag == true -> {other_flag_1 == false;
                 other_flag_2 == false;
                 other_flag_3 == false;};
}

Note that when your constraints are Boolean expressions, it’s the same as the logically ANDing them into one Boolean expression

constraint example {
flag == true ->  other_flag_1 == false &&
                 other_flag_2 == false &&
                 other_flag_3 == false;
}