SystemVerilog constraint implication with multiple variable

[ABD_91]

You could write the multiple constraints using if-else constraint as well ::

constraint example {  if ( flag == true ) 
                        {
                           //  Add  multiple  constraints  here
                           other_flag_1 == false;
                           other_flag_2 == false;
                           other_flag_3 == false;
                        }
                     }