Systemverilog assertions

SystemVerilog
,
5

In reply to dave_59:
testbench http://SystemVerilog.us/vf/a4bc.sv


 // "When a is equal to any value from 0 to 31 ,then in the next 4 cycles ,
  //either b or c should be equal to what a was in the first cycle, 
  // and a cannot be the same as it was in the first cycle."
 property p_a4bc;
    int v;
    @(posedge clk) (a inside {[0:31]}, v = a) |-> ##[1:4] (v == b || v==c) and 
                                                  ##1 (a != v)[*4];
 endproperty
 ap_p_a4bc: assert property(p_a4bc);

1871×903 118 KB

http://SystemVerilog.us/vf/a4bc.sv
Image: http://SystemVerilog.us/vf/a4bc.png

Ben Cohen
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