Systemverilog assertion

SystemVerilog
,
6

In reply to wangjiawen:
Sorry, but I made a mistake.
Assertions need to be tested!!!
we’re human :)


//  ap_abc3 DOES NOT WORK as I expressed because 
ap_abc3: assert property(@(posedge clk) 
			 first_match(a ##1 (b[=1] and c[=1])) |-> d);  

ap_abc3_equiv: assert property(@(posedge clk) 
             first_match(a ##1 (!b[*0:$] ##1 b ##1 !b[*0:$] and 
                    !c[*0:$] ##1 c ##1 !c[*0:$])) |-> d);  
// Then the !b[*0:$] gives you the option of a thread !b[*0], 
//  thus not a requirement for for a follow-up "b" to be equal to 0. 
//----- WHAT IS NEEDED INSTEAD 
ap_abc2_want: assert property(@(posedge clk) 
                   first_match(a ##1 (!b[*0:$] ##1 b ##1 !b[*1:$] and 
                           !c[*0:$] ##1 c ##1 !c[*1:$] )) |-> $past(d));

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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