In reply to ben@SystemVerilog.us:
sorry for late Ben.
module Testbench;
// DUT signals
logic clk;
logic GntA=0;
logic Busy=0;
logic DRdy=0;
logic Done=0;
initial begin
clk = 0;
end
// Instantiate assertion checkers
initial begin
// Initialize signals
repeat(3)
@(posedge clk);
/////////////////////////////////////////////////////////////////
GntA = 1;
repeat(1)
@(posedge clk);
GntA = 0;
Busy = 1;
DRdy = 1;
repeat(1)
@(posedge clk);
Done =1;
repeat(1)
@(posedge clk);
Done =0;
Busy =0;
DRdy = 0;
repeat(14)
@(posedge clk);
// Finish simulation
#100;
$finish;
end
always #1 clk = ~clk;
initial begin
$shm_open("wave.shm");
$shm_probe("AS");
end
property BPE1;
@(posedge clk)
(GntA) |=> Busy[*1:2] throughout DRdy ##0 Done;
endproperty
CHK_BPE1 : assert property (BPE1);
property BPE2;
@(posedge clk)
(GntA) |=> DRdy throughout Busy[*1:2] ##0 Done;
endproperty
CHK_BPE2 : assert property (BPE2);
endmodule
From BPE1, I get the error " Expected a verilog expression as operand to throughout operator."